FPGAs provide advanced capabilities that traditional processors offer and additionally offer hardware acceleration capabilities. Unfortunately, lack of infrastructure has relegated FPGAs to being second-class citizens rather than being autonomous nodes in a cluster. This stands in the way of a truly distributed/heterogenous computing model. The Configurable network Protocol Accelerator (COPA) project addresses this challenge by providing a framework that integrates communication with computation on an FPGA platform. COPA has been implemented on a Stratix10 FPGA (SOC and non-SOC) and a PCIe Stratix10 attached to a Xeon host. Multiple FPGAs attach to a standard 100GigE switching network with the ability to mix-and-match the FPGA type that attaches to the network. A software stack that exposes the acceleration and networking capabilities to the application is a key feature of COPA. Obviously, extending a network API to include acceleration support is easier than extending a standard acceleration API to support network communication. Hence, COPA software supports OFI with extensions for exposing the various acceleration modes to the application. This presentation will provide a short overview of COPA and the different acceleration modes that it supports along with the OFI extensions in place to invoke them.
Andriy Kot is a Software Development Engineer at Intel. He works on enabling new network hardware including accelerators. Previously, he was part of a team that launched and supported the Blue Waters supercomputer at the National Center for Supercomputing Applications at the University of Illinois in Urbana-Champaign. Before, he was a post-doc in the Old Dominion University continuing his research on out-of-core and effective computing and run-time systems in HPC. Andriy holds a Ph.D. in Computer Science from the College of William and Mary as well as M.S. in Computer Science and Computer Engineering. His interests include HPC middleware, networks and accelerators, extreme scale computing, run-time systems and programming models and software/hardware co-design.