Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processors and devices such as accelerators, memory buffers and smart IO adapters. It is designed to address the needs of heterogeneous high performance processing systems, as well as server systems with disaggregated memory and IO resources. In this session, the team will describe the capabilities of CXL, and will also discuss the 2nd generation of CXL (CXL 2.0) with the additional features it will bring to HPC platforms.
Steve is currently the Director of Processor Interconnect Architecture, leading architecture development of both internal and external interconnects for Intel processors. He is primarily focused on server processors, but often leads development of technologies that span multiple segments. Steve was one of the key contributors to the Compute Express Link (CXL) architecture. Prior to his current role, Steve has served in a variety of capacities at Intel, including leadership roles in both client and server processor architecture. Prior to Intel, Steve contributed to several generations of VAX, Alpha and Itanium server systems at Digital Equipment Corp., Compaq Computer Co. and Hewlett-Packard.
Jim Pappas is the Director of Technology Initiatives at Intel Corporation. In this role, Jim is responsible to establish broad industry ecosystems that comply with new technologies in the areas of Datacenter I/O, Energy Efficient Computing, Solid State Storage, and Persistent Memory. Jim has founded, or served on several organizations in these areas including: PCI Special Interest Group, Universal Serial Bus (USB), Storage Networking Industry Association (SNIA), InfiniBand Trade Association (IBTA), Open Fabrics Alliance (OFA), The Green Grid (TGG), Compute Express Link (CXL), and many others. Jim has over 30 years of experience in the computer industry. He has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies. He has spoken at dozens of major industry events and holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.
Rob is a Principal Engineer at Intel Corporation in the I/O Technology and Standards Group. His expertise is in cache coherence protocols and memory interfaces for server products. As a participant in the CXL Consortium, he has lead training and has authored areas of the specification related to transaction and link layers. As co-chair of the CXL Protocol Working Group, he is currently working on the next generation specification development.