Enabling intelligent endpoints with COPA FPGAs


With the increase in edge devices and the resulting explosion in data, communication with backend nodes is becoming prohibitively expensive. The goal is to minimize data movement and perform computation at the edge devices in a decentralized or a hybrid fashion. FPGAs are an ideal fit to meet the power and space restrictions of edge nodes. The flexibility of FPGAs is helpful as algorithms/data sets continue to evolve. However, FPGAs must not only perform computation but must do so in a distributed fashion that require communicating with each other at scale. They must also use acceleration as an integral part of this communication. Intel’s COnfigurable network Protocol Accelerator (COPA) enables FPGAs to be deployed in a distributed fashion and directly attached to the network. The COPA framework provides a modular architecture that can be configured with various accelerator modules. Both inline (bump-in-the-wire) and lookaside acceleration capabilities are supported – this is an important feature for distributed (autonomous) FPGAs communicating over a network. In this talk, we provide an overview of the COPA framework. The hardware component of COPA provides the necessary networking/accelerator infrastructure. The software component abstracts the underlying FPGAs from the application using an open standard interface. The talk will also cover a few usage models in a large-scale system wherein COPA enabled FPGAs could be deployed as intelligent endpoints, enable resource disaggregation, and allow computation to be performed closer to where the data originates or resides.


Venkata Krishnan

Dr. Venkata Krishnan is a Principal Engineer at Intel Corporation where he focuses on various aspects of microprocessor architecture and data center/HPC networking. He leads a team focused on enabling FPGAs to act as independent accelerator nodes directly attached to the network. He holds a B.Tech from IIT Madras and a PhD from Univ. of Illinois in Computer Science. Prior to joining Intel, he was a fellow at AMD, research scientist at DEShaw research and CTO of Dolphin Interconnect. He has also served as member/chair of SIG technical committees/panels and conference program committees.