Reverse Time Migration takes advantage of the finite-difference method (FD) to perform the numerical approximations for the acoustic wave equation. Stencil computation applied to this numerical method represents a computational bottleneck when developing RTM applications, and therefore needs to be optimized to guarantee timely results and efficiency when allocating resources for hydrocarbon exploration. This article presents a migration experience from a CUDA-based RTM source code to Data-Parallel C++ (DPC++) using Intel DPC++ Compatibility Tool (DPCT). Migrated source code is proven to be easier to maintain, as it unifies the algorithm execution flow for our application in a unique structure. Besides migration experience, we could easily explore memory management, achieving twice the performance and an arithmetic intensity 4,9x higher than the first version.

Migrating and Tuning a CUDA-Based Stencil Computation

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Clicia Pinto, Performance Engineer, SENAI CIMATEC

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The unprecedented influx of data is helping drive the evolution of HPC environments today. From converged AI and HPC workloads to multipurpose systems to diverse architectures, we’re asking more of our HPC systems than ever before. Turn that complexity into opportunity with Intel’s HPC Portfolio – including the latest Intel® Xeon® Scalable processors, discrete GPUs and powerful software tools – and accelerate your possibilities with HPC.

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Trish Damkroger, VP and GM, High Performance Computing Group, Intel Corporation

Real-world applications are evolving and becoming more diverse with data intense workloads delivering new science opportunities. 3rd Generation Intel® Xeon® Scalable processors, Intel® Optane™ persistent memory, and Intel accelerators provide the features, flexibility and performance required. This session will provide an update on Intel’s portfolio, technologies, features and plans.

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Jeff Watters, Director of the HPC Portfolio and Strategic Engagements, Intel Corporation

From faster simulations for new drug discovery to computational fluid dynamics (CFD) to accelerate product engineering to empowering cardiologists with highly accurate personalized human heart models, HPC has and is poised to positively impact every human on earth. HPC in the cloud has enabled extending the reach and impact of HPC for everyone, whether it is for those with on-prem systems or new users of HPC. Leaders in the forefront of HPC in the Cloud will discuss the benefits of today’s computational capabilities to society. In this panel, hear from leading cloud service providers on how Intel’s portfolio of solutions including 3rd Gen Intel® Xeon® Scalable Processors, Optane Persistent Memory, Distributed Asynchronous Object Storage (DAOS) and Intel® SGX are providing the performance, flexibility and innovation to achieve what was impossible just a few years ago.

HPC in the Cloud: Extending the Reach and Impact of HPC for Everyone

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Bill Magro, HPC Chief Technologist, Google

Nidhi Chappell, Head of Product, Specialized Azure Compute, Microsoft

Karan Batta, Vice President, Product, Oracle Cloud Infrastructure

Come learn about the oneAPI specification, open source and cross architecture standard. Open and multi-vendor is critical as we progress in an open heterogeneous world. Hear from representatives at Apache MXNet PPMC, Xilinx, Codeplay, and Heidelberg University, who are working on open standards, oneAPI and SYCL to drive development for the HPC and AI markets.

Standards Driven Heterogenous Programming with oneAPI

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Jeff McVeigh, VP and GM, Data Center XPU Products & Solutions, Intel Corporation

Sheng Zha, Apache MXNet PPMC

Ronan Keryell, Principal Software Engineer, Xilinx Research Labs

Andrew Richards, CEO and Co-Founder, Codeplay

Aksel Alpay, Research Software Engineer, Heidelberg University

The convergence of system architectures supporting modeling and simulation, data analytics, and artificial intelligence workloads is generating unprecedented demands on the high-performance interconnects that serve as the backbone of the resulting system implementations. Cornelis Networks is focused on delivering highly optimized interconnect solutions capable of unleashing the processing potential inherent in clusters from small to extreme scale. The company is a spin-out from Intel's interconnect business bringing with it the end-to-end highly scalable Omni-Path fabric product line which currently features in 20% of the Top100 system list. Cornelis Networks is the only independent supplier of scalable fabrics for HPC/HPDA/AI clusters and delivers highly competitive performance and compelling price/performance. The talk will cover the additional challenges for Omni-Path fabrics in mixed workload HPC/IA systems and how these are being addressed with short term innovations and in future roadmaps. Consideration will also be given to the effect of AI acceleration in 3rd generation Intel® Xeon® Scalable processors and the additional requirements of programming frameworks in the AI world. Finally, the talk will cover the work of Cornelis Networks within the Open Fabrics Alliance in particular with Libfabric and Open Fabric Interface.

Cornelis Networks Omni-Path Express™ (OPX) Technology

John K. Lee, Sr. Director of HPC Business & Platform Strategy, Data Platforms Group, Intel Corporation

Philip A. Murphy Jr., Co-Founder, Chief Executive Officer, Cornelis Networks

Intel and Google HPC experts share our vision for how our collaboration on DAOS on GCP can fill a critical gap for high-performance storage in the cloud.

Bringing DAOS to the Cloud

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Kelsey Prantis, Senior DAOS Engineering Manager, Intel Corporation

Ilias Katsardis, HPC Solutions Lead, Customer Engineering team (EMEA) at Google Cloud

Dean Hildebrand, Technical Director, Office of the CTO at Google Cloud

Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low-latency connectivity between host processors and devices such as accelerators, memory buffers and smart IO adapters. It is designed to address the needs of heterogeneous high performance processing systems, as well as server systems with disaggregated memory and IO resources. In this session, the team will describe the capabilities of CXL, and will also discuss the 2nd generation of CXL (CXL 2.0) with the additional features it will bring to HPC platforms.

CXL Fireside Chat

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Stephen Van Doren, Intel Fellow, Director of Processor Interconnect Architecture, Intel Corporation

Jim Pappas, CXL Consortium Chairman and Director of Technology Initiatives, Intel Corporation

Robert Blankenship, Principal Engineer, Intel Corporation

Fireside chat from the development team about the Intel System Server D50TNP for HPC and AI. Supporting 3rd Gen Intel® Xeon® Scalable processors and new features like PCIe Gen 4.0, this system is aimed at helping HPC users by offering multiple module types to address HPC tasks. It supports compute modules for computationally intense workloads, management modules for a typical HPC rack, storage modules offering 1/2 PB of PCIe 4.0 based storage in a single module and 1PB in 2U, and a 2U chassis that supports two Intel Xeon processors and four low profile and four FHFL DW PCIe cards.

Intel System Server D50TNP for HPC

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Scott Misage, Manager Product Development & Architecture, Intel Corporation

Brian Caslis, Product Line Manager, Intel Corporation

Jim Russell, Project Design Manager, Intel Corporation

Data growth and the converged use of HPC and AI are challenging organizations to find new ways to transform their digital infrastructure to maintain competitiveness and to drive growth and discovery. From Exascale-class systems to enterprise datacenters, HPE and Intel are partnering to deliver a robust portfolio of high-performance computing solutions to accelerate discovery and reduce time to insight. In this session, we’ll look at the latest trends in high performance computing and how the partnership between HPE and Intel is poised to deliver powerful and diverse solutions to support our customers mission-critical research and discovery.

Powerful HPC Partnership Between HPE and Intel

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Bill Mannel, VP & GM of HPC and MCS, Hewlett Packard Enterprise

The ability to pay-per-use for HPC resources in the cloud makes its strategic advantages affordable for almost any organization, including enterprise lines of business. And while some organizations may not be comfortable with every type of cloud computing, sharing HPC compute and storage resources over a network is hardly news to veteran IT shops. Large organizations have long shared HPC resources in various models — including infrastructure as a service (IaaS), platform as a service (PaaS) and software as a service (SaaS) — and continue to pioneer new ways to spread the HPC wealth while defraying the costs of running these advanced computing systems. As more and different types of users rush to leverage advanced computing resources, the hybrid cloud model continues to be ideally suited for HPC, AI and HPDA.

Considerations for HPC and AI in the Cloud

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Binay Ackalloor, Director, HPC Cloud, Cloud & Enterprise Solutions Group, Intel Corporation

Dr. Jay Boisseau, AI and HPC Technology Strategist, Dell Technologies

Scala Computing provides a secure, hyper-scalable platform allowing users to run their HPC applications on the Cloud. Scala’s goal was to optimize the ns3 application to provide Network Vendors and HyperScalars an extremely powerful simulation platform. Our solutions allow users to run extensive network simulations determining proper network topology, stack solutions and equipment configuration determining how machine learning algorithms affect data center efficiency for their enormous user-base. Simulation speed is of the essence meaning, compute clusters with proper high-speed compute and memory ratio solutions are extremely important to providing desired results. This is where Scala’s use of AWS provided not only proper instances for configuring HPC clusters, but many additional solutions in cluster deployment and security. We evaluated many instance types and determined AWS Z1Ds using the Intel Xeon Scalable processor was the perfect choice. The sustained core frequency of 4 GHz and 384 GB of RAM allowed Scala to understand what consistent performance can be achieved with various optimizations. Parallelizing compute capabilities using MPI was key to running large scale simulations without simulation completion times increasing to undesirable levels where running “what-if” scenarios became too time consuming. Scala Computing spent significant time analyzing various MPI solutions to determine the best results for our customers. After many tests across numerous configurations, Intel’s iMPI solution was a clear winner. The partnership using both AWS and Intel solutions allowed Scala to have one of the first efficient Discrete Event Network Simulators to run at Data Center Scale.

Accelerate High Performance Computing on the Cloud

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Sam Rahman, CTO, Scala Computing

In this talk, we will discuss how enterprises are experiencing substantial productivity by migrating  to the atNorth hybrid HPC as a Service (HPCaaS) by leveraging the best of on-premise and cloud. We will discuss a specific use case where we used an Intel Select Solution on 2nd Generation Intel® Xeon® Scalable processor (Cascade Lake) and validated on 3rd Generation Intel® Xeon® Scalable processor (Ice Lake) to enable our customer to have the best price/performance while also ensuring that the customer’s workload was perfectly portable between their on-premise environment and the cloud. The atNorth HPCaaS is also available for channel partners via the Intel® Solutions Marketplace.

HPC Productivity Increase with Hybrid HPCaaS

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Guy D'Hauwers, VP HPC & AI, atNorth

Molecular dynamics (MD) provides an indispensable computational methodology for understanding biomolecular systems at atomic level detail, accessing spatial and temporal resolutions that are not available to purely experimental approaches. As computational power increases, MD techniques are ever more useful for tackling significant biomedically relevant challenges, such as illuminating details of the infection mechanism by the SARS-CoV-2 virus that causes COVID-19 and guiding computational approaches for the development of new pharmaceuticals and therapeutics. NAMD is an important MD application to the biomedical community, offering excellent performance on a range of platforms from desktop workstations up through the largest leadership class supercomputers. Although NAMD has been GPU-accelerated for more than a decade, it is important to introduce cross-platform support to leverage the capabilities of the upcoming DOE supercomputers, in particular, the Argonne Aurora supercomputer which is to be accelerated by Intel GPUs. This presentation discusses the ongoing NAMD development efforts to improve its cross-platform support by adopting oneAPI, which involves porting its many CUDA kernels to DPC++ with the Intel DPC++ Compatibility Tool and using the Intel VTune profiler to improve GPU utilization and overall performance of the new DPC++ kernels.

XPU Support for the NAMD Molecular Dynamics Application with oneAPI

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Dr. David J. Hardy, Theoretical and Computational Biophysics Group, Beckman Institute, University of Illinois at Urbana-Champaign

Ever wonder how those cool scientific images are created? Come join Dr. Paul Navrátil, Ph.D., Research Scientist, Director of Visualization at the Texas Advanced Computing Center, as he walks through the features of Intel® oneAPI Base & Rendering Toolkit, their benefits and how they are used to create images from massive data sets. These stunning images inform the latest scientific research. Paul will share how doing data analysis at scale can stress modern hardware architectures and how they overcame these challenges using Intel software. The results, using the Frontera supercomputer and 3rd Generation Intel® Xeon® Scalable processors to run the data analysis and scientific visualization, are beautifully rendered, massive images of a black hole collision, EU weather, the largest environment weather map ever rendered and more.

Utilizing the oneAPI Rendering Toolkit to Enhance Scientific Discovery

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Paul Navrátil, Ph.D., Research Scientist, Director of Visualization, Texas Advanced Computing Center

How Mellanox HDR and 3rd Gen Intel® Xeon® Scalable processors produce best in class performance for HPC applications. Performance data will be shared showing the benefits for upgrading to HDR and 3rd Gen Intel Xeon Scalable processors along with the features and tips to enable this.

Ice Lake with Mellanox Interconnect Solutions

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Gilad Shainer, Senior Vice President Marketing, NVIDIA

The parallelized large-eddy model code PALM, which runs at the Zuse Institute Berlin, is used by researchers to simulate the city climate with the goal of improving air quality in the German capital. For fine-granular resolutions of the application's compute domain, the memory footprint easily exceeds the capacity of a usual cluster node's main memory. Using Optane memory, the number of required cluster nodes for a particular simulation can be reduced. While using Optane's Memory Mode allows flawless usage of the large capacity with only small performance loss, the AppDirect Mode enables further optimizations. We show that a partitioning of the application between DRAM and Optane memory can speedup the essential Multigrid solver part of the application over the Memory Mode by up to 8%. We also note that the gained speedup is lost, when data must be transferred between the two memory types. The use case reveals the challenge of data partitioning and optimizing the data transfers between different memory types on heterogeneous memory systems.

Optimizing a Memory-Intensive Simulation Code for Heterogenous Optane Memory Systems

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Steffen Christgau, HPC Consultant, Zuse Institute Berlin

The Intel Quantum Computing Team develops application-oriented workloads and uses them to drive the design of the quantum computing system architecture. This talk shows an example of the execution of an Intel-developed Materials Design workload that resulted in the identification and implementation of a new quantum instruction. This result also had implications for designing the functionality of the rest of the quantum computing system stack.

Intel Quantum Computing: An Example of Workload-Driven System Design

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Anne Matsuura, Ph.D., Director, Quantum Applications & Architecture, Intel Corporation

In a recent survey of manufacturing customers, greater than 50% stated their top challenge is to reduce their design time for faster time to market and time to solution. Identifying the right processor platforms and technologies for HPC-enabled simulation is key to solving this challenge. Join us to hear about how Ansys and Intel have long collaborated to address the customer needs – both in identification of the right platforms and technologies, and in technical partnership to deliver most optimized performance for customer’s Ansys applications. In this technical talk, we will discuss current optimizations Ansys applications deliver with 3rd Generation Intel® Xeon® Scalable processors and Intel® Optane® SSD technologies, and in addition focus on the key considerations, and selection guidelines in choosing the right platform technologies – processors, memory, and storage for customers to meet design needs and time to market business imperatives.

Best Practices in Selection of the Latest Intel Technologies for HPC-Enabled Simulations

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Wim Slagter, Strategic Partnerships Director, Ansys

Traders and Portfolio Managers in hedge funds and investment banks managing complex derivative portfolios are often not able to view their risks in real time as risk calculations are too computationally demanding. Traditional valuation techniques often use expensive methods like numerical integration and Monte Carlo simulation. We take a conventional model for the valuation of credit options and train an Artificial Neural Network (ANN) to perform the same valuations achieving a speedup of 700x. An improvement of 700x opens up the possibility for financial institutions to move from overnight batch risk calculations to live risk calculations transforming the ways in which they can manage risk. The speedup is achieved by a combination of switching from numerical integration to ANN and using Intel Optimized version of TensorFlow (AVX512) on Intel's newest Ice Lake processors.

Accelerating Derivative Valuations

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Sebastian Hahn, AI/ML Lead, Quantifi

As a key OEM in HPC, Atos must constantly study new paths to provide the best services, architecture and software environment for the current and future needs of its customers. Today, one of the biggest challenges is programming and efficiently using a growing number of architectures including GPUs or FPGAs. In this talk, Atos will disclose its first evaluations and analysis of the standards driven and open community oneAPI initiative, leveraging Intel’s implementation and the possible capacities of this standard to tackle users’ problems while eliminating vendor lock in. Join us to hear about our experiences and see our work targeting CPUs and GPUs with oneAPI.

Address Exascale Challenges by Leveraging oneAPI Industry Standard

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David Goudin, Atos HPC Applications Expert

With an ever-increasing number of hardware architectures with numerous processor and accelerator options to choose from, finding the right system architecture for future high performance computing systems is getting an increasingly complex task. It requires a forward-looking understanding of the users’ and applications’ evolving needs together with an understanding of the selections’ performance, power, and cost implications. To address this challenge, the Future Computing Group at Leibniz Supercomputing Centre (LRZ) works closely with Intel and MEGWARE to plan, install and operate a wide variety of latest technology hardware for evaluation. In the presentation, we will explain the configuration of the latest upgrade to the test cluster, which is based on 3rd Generation Intel® Xeon® Scalable processors (both Cooper Lake and Ice Lake based) and Intel® Optane™ Persistent Memory. In addition, the systems are already prepared for Intel® Xe GPGPUs and will be upgraded once they become available. We will go into further detail, how the workloads at LRZ are evolving and explain our reasoning for the system’s architecture based on the requirements of different use cases. By using DAOS, Intel-optimized software frameworks and the oneAPI toolkit, the system also makes an ideal case for a flexible approach to tackling both current HPC tasks and emerging workloads in the field of data analytics and machine learning. Only by joining forces and expertise, LRZ, MEGWARE and Intel together help to ensure that HPC centers continue to work at the forefront of technology while providing the best computing infrastructures for their scientific customers.

A Partnership for Future HPC Technologies Exploration

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Josef Weidendorfer, Head of Future Computing Group, Leibniz Supercomputing Centre

Axel Auweter, Chief Technology Officer, MEGWARE

What leaders need during a crisis is not a predefined response plan but behaviors and mindsets that will prevent them from overreacting and help them look ahead. In unfamiliar and uncertain situations, effective responses are largely improvised. They might span a wide range of actions, not just temporary moves but also adjustments to ongoing business practices, which can be beneficial to maintain even after the crisis has passed. Leadership practices that can help respond effectively are: organizing via network, displaying calm and optimism, making decisions amid uncertainty, demonstrating empathy, and communicating effectively. The pandemic deepened pre-existing inequalities, exposing vulnerabilities in social, political, and economic systems. Across every sphere, from health to the economy, security to social protection, the impact was exacerbated for women and girls. Hear from key HPC leaders on how they enabled their community and their customers & partners during this unprecedented crisis.

Observations & Learnings from Industry Leaders

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Aswathy Nair, Strategic Relationship Manager, HPC ISVs, Intel Corporation

Cristin Merritt, Change Management Specialist, Alces Flight

Fouzhan Hosseini, Software Engineer, NAG

Tiffany Cook, Partnerships and Public Relations Manager, Convergent Science

Paula Olaya Ph.D. Student in Computer Science, University of Tennessee, Knoxville

The proliferation of machine learning services in the last few years has raised privacy concerns. Homomorphic encryption (HE) enables inference using encrypted data but it incurs 100x-10,000x memory and runtime overhead. Secure deep neural network (DNN) inference using HE is currently limited by computing and memory requirements, with frameworks requiring hundreds of gigabytes of DRAM to evaluate small models. To overcome these limitations, we explore the feasibility of leveraging hybrid memory systems comprised of DRAM and persistent memory subsystems. In particular, we explore the recently-released Intel® Optane™ PMem to run large DNNs such as MobileNetV2 (in its largest variant) and ResNet-50 for the first time ever. We present an in-depth analysis of the efficiency of the executions with different hardware and software configurations. Our results conclude that DNN inference using HE yields friendly access patterns for this memory configuration, yielding efficient executions.

Breaking the DRAM Size Wall for DNN Inference and Homomorphic Encryption

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Dr. Antonio J. Peña

The National Science Foundation (NSF) has awarded the San Diego Supercomputer Center (SDSC) at UC San Diego a $5 million grant to acquire a high-performance computer, Voyager, for conducting artificial intelligence (AI) research across a wide swath of science and engineering domains. An equivalent amount of additional NSF funding is expected to support community engagement and operation of the resource. As AI/DL research workloads increase in size, complexity and demand, there’s a growing need, particularly for increased training performance and efficiencies. SDSC has selected the Intel company’s Habana Labs accelerators, designed expressly to drive efficiencies in the data center, to provide high-performance AI compute for its experimental Voyager supercomputer. In this fireside chat we will discuss why SDSC selected Habana AI accelerators for Voyager and how this new class of AI compute solutions will enhance SDSC’s AI research capability.

Purpose-Built AI Accelerators Deployment for High Performance Computing

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Stephan Gillich, Director of Artificial Intelligence - GTM, Datacenter Solutions & Sales, Intel Corporation

Eitan Medina, Habana Labs, an Intel Company

Amit Majumdar, Division Director, Data Enabled Scientific Computing, San Diego Supercomputer Center, University of California San Diego

Intel has been building an entirely open source software ecosystem for data-centric computing, fully optimized for Intel® architecture and non-volatile memory (NVM) technologies, including Intel® Optane™ DC persistent memory and Intel® Optane™ DC SSDs. Distributed Asynchronous Object Storage (DAOS) is the foundation of the Intel Exascale storage stack. DAOS is an open source software-defined scale-out object store that provides high bandwidth, low latency, and high I/O operations per second (IOPS) storage containers to HPC applications. It enables next-generation data-centric workflows that combine simulation, data analytics, and AI. 

Solving I/O Bottleneck with DAOS and PMEM

Andrey Kudryavtsev, DAOS Product Manager

With the increase in edge devices and the resulting explosion in data, communication with backend nodes is becoming prohibitively expensive. The goal is to minimize data movement and perform computation at the edge devices in a decentralized or a hybrid fashion. 

FPGAs are an ideal fit to meet the power and space restrictions of edge nodes. The flexibility of FPGAs is helpful as algorithms/data sets continue to evolve. However, FPGAs must not only perform computation but must do so in a distributed fashion that require communicating with each other at scale. They must also use acceleration as an integral part of this communication. Intel’s COnfigurable network Protocol Accelerator (COPA) enables FPGAs to be deployed in a distributed fashion and directly attached to the network. The COPA framework provides a modular architecture that can be configured with various accelerator modules. Both inline (bump-in-the-wire) and lookaside acceleration capabilities are supported – this is an important feature for distributed (autonomous) FPGAs communicating over a network. 

In this talk, we provide an overview of the COPA framework. The hardware component of COPA provides the necessary networking/accelerator infrastructure. The software component abstracts the underlying FPGAs from the application using an open standard interface. The talk will also cover a few usage models in a large-scale system wherein COPA enabled FPGAs could be deployed as intelligent endpoints, enable resource disaggregation, and allow computation to be performed closer to where the data originates or resides.

Enabling intelligent endpoints with COPA FPGAs

Venkata Krishnan

FPGAs provide advanced capabilities that traditional processors offer and additionally offer hardware acceleration capabilities. Unfortunately, lack of infrastructure has relegated FPGAs to being second-class citizens rather than being autonomous nodes in a cluster. This stands in the way of a truly distributed/heterogenous computing model. 

The Configurable network Protocol Accelerator (COPA) project addresses this challenge by providing a framework that integrates communication with computation on an FPGA platform. COPA has been implemented on a Stratix10 FPGA (SOC and non-SOC) and a PCIe Stratix10 attached to a Xeon host. Multiple FPGAs attach to a standard 100GigE switching network with the ability to mix-and-match the FPGA type that attaches to the network. 

A software stack that exposes the acceleration and networking capabilities to the application is a key feature of COPA. Obviously, extending a network API to include acceleration support is easier than extending a standard acceleration API to support network communication. Hence, COPA software supports OFI with extensions for exposing the various acceleration modes to the application. 

This presentation will provide a short overview of COPA and the different acceleration modes that it supports along with the OFI extensions in place to invoke them.

Enhancing OFI (Open Fabric Interfaces) networking interface to support COPA acceleration capabilities 

Sessions

Migrating and Tuning a CUDA-Based Stencil Computation to DPC++

Abstract

Speakers

Clicia Pinto, Performance Engineer, SENAI CIMATEC