Come learn about the oneAPI specification, open source and cross architecture standard. Open and multi-vendor is critical as we progress in an open heterogeneous world. Hear from representatives at Apache MXNet PPMC, Xilinx, Codeplay, and Heidelberg University, who are working on open standards, oneAPI and SYCL to drive development for the HPC and AI markets.
Jeff McVeigh is Vice President of Intel Architecture, Graphics and Software, where he also serves as the General Manager of Data Center XPU Products & Solutions. McVeigh’s career has spanned research, product development and business creation, with the common thread of enabling exceptional visual computing experiences for Intel customers. Intel is committed to enriching the lives of every person on earth through delivery of a heterogeneous mix of scalar, vector, matrix and spatial architectures deployed as XPU sockets: CPUs, GPUs, specialized accelerators, and FPGAs. These diverse architectures require a unified programming model to achieve productive performance and allow developers to solve previously unsolvable problems. McVeigh’s team is responsible for the oneAPI industry initiative and Intel product to unleash the ecosystem from proprietary accelerated-computing solutions. He brings a software and developer-oriented mindset to Intel’s data center GPU business, where his team utilizes deep workload expertise, scalable ecosystem enabling, and the oneAPI solution to drive Xeon and discrete GPU product lines for HPC, AI, enterprise, and cloud media customers. McVeigh holds a bachelor’s degree in electrical engineering from Duke University and a Ph.D. in electrical and computer engineering from Carnegie Mellon University. He has been issued more than 20 patents and has published multiple papers, primarily in the field of video compression and processing. He lives in Portland, Oregon, and enjoys skiing, hiking, mountaineering, and spending time with his wife, two daughters, and dog.
Sheng Zha is a committer and PPMC member of Apache MXNet (Incubating), a former steering committee member of Linux AI Foundation ONNX, a member of the Consortium for Python Data API Standard, and a senior applied scientist at Amazon. In his research, Sheng focuses on the intersection between deep learning based natural language processing and computing systems, with the aim of enabling large-scale and accessible representation learning.
Ronan Keryell is principal software engineer at Xilinx Research Labs where he works on the SYCL C++-based programming model for heterogeneous system like FPGA and CGRA. He is also the specification editor of the SYCL standard and member of the SYCL, SPIR & OpenCL standard committees in the Khronos Group. He participates also to the ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment. He worked in the academia on automatic parallelization, compilation of HPF, high-level synthesis, co-design, networking and secure computing. He was co-founder of 3 start-ups, mainly in High-Performance Computing, was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.
CEO and co-founder of Codeplay, Andrew started his career writing video games in the days of 8-bit computers, progressing to become a lead games programmer at Eutechnyx™. Andrew started Codeplay to produce cross-platform compilers and for games consoles, special-purpose processors and GPUs Codeplay now is the leading software developer for the SYCL open standard. As well as being CEO and Founder of Codeplay Software Ltd, Andrew is also the Chair of the Software working group of the HSA Foundation™ and former Chair of the SYCL™ for OpenCL™ sub-group of the Khronos® Group.
Aksel Alpay is a researcher and software engineer from Heidelberg University, where he works on high performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language. Previously, he held a position as research software engineer and staff in the HPC group at the Heidelberg University Computing Center.